During integrated circuit manufacturing using semiconductor processing and equipment, a common manufacturing goal is to provide circuit devices with a desired performance within a range of acceptable performance. Certain device performance criteria are often used to establish that the devices completed on a semiconductor wafer do, or do not, meet the established criteria for an acceptable wafer. For example, when manufacturing integrated circuits including metal oxide semiconductor field effect transistor (MOSFET) devices on semiconductor wafers, the drain current measured when a MOSFET is in a saturation mode (Idsat) is one objective measure of device performance that may be evaluated. Other measurable criteria may be selected, such as a threshold voltage (Vt), for example.
In the known approaches, this testing is performed after the wafer is completed through the semiconductor processing, but prior to the dicing of the individual integrated circuit devices (ICs) from the semiconductor wafer, at a stage known as the wafer acceptance test (“WAT”). At WAT, probes may be placed onto pads coupled to various active devices within the integrated circuits that are formed on the semiconductor wafer, and certain measurements may be made. If the device performance measured at WAT is not acceptable, then the wafer, which has been processed through many expensive and time consuming processing steps, and the materials used to perform the semiconductor manufacturing process, are wasted. Further, the determination of which steps or processes are causing the unacceptable performance may be difficult, so reduction of or elimination of further defective wafers is also difficult. The testing at the WAT station is also costly and time consuming, and testing numerous defective wafers (wafers with devices that will not meet the range of acceptable performance criteria) is also inefficient.
A continuing need thus exists for methods and systems to evaluate device performance during semiconductor processing and to accurately predict when the completed devices will, or will not, have acceptable performance. Improvements are needed to increase manufacturing yields, and to reduce the waste of time and waste of expensive materials in semiconductor manufacturing currently experienced when using the known methods.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.